This invention relates to chemically enhanced ion beam etching, and in particular, to using a focused ion beam to selectively etch inter layer dielectrics deposited during integrated circuit fabrication.
Integrated circuits are fabricated by growing, depositing, diffusing, and etching thin layers of conductors, insulators, and semiconductors onto a substrate of a semiconductor material, such as silicon or gallium arsenide wafer. To keep the fabrication processes operating properly, or to diagnose and correct the process when a defect does occur, process engineers must be able to quickly examine the various processed layers.
A primary tool used for examining, analyzing, and repairing processing layers is a focused ion beam (FIB) system. FIB systems improve manufacturing yields by identifying and analyzing defects on in-process wafers, allowing the source of defects to be located and corrected. For example, layers can be sputter-etched by an FIB system to expose underlying layers for observation and testing, or cross sections can be cut to expose the edges of multiple layers to observe layer thickness, uniformity, and inclusions. FIB systems can also form images of microscopic features and can be used to repair or test integrated circuits by depositing conductive or insulating material.
The processing layers exposed by the removal of covering material using FIB etching can be examined either using the imaging capability of the FIB system, or using a scanning electron microscope (SEM). The electron beam of an SEM causes less sample damage than does the ion beam of an FIB system, and the SEM is typically capable of forming a higher resolution image. SEMs are often available within the same vacuum chamber as an FIB system, such as in the DualBeam.TM. family of FIB Systems from FEI Company, the assignee of the present invention. In such a system, a cross section of the processing layers can be milled and then observed within the same vacuum chamber, with little or no movement of the sample. Such a system is particularly well suited to process control applications, where specimens must be analyzed quickly to provide feedback to a production line.
Many of the layers in an integrated circuit are composed of relatively non-conductive materials that are used to separate conductive layers or as passivation and protection layers for the chip. Such layers are known as interlayer dielectrics (ILDs). ILDs include deposited oxides of various densities, thermal oxides, spun on glass, and nitrides. When ILDs are cross-sectioned with a focused ion beam and viewed, it is often impossible to distinguish among them. Thus, individual layer thickness cannot be determined and process engineers cannot isolate defects to a particular layer.
To distinguish between different ILD layers, it has been necessary to remove the specimen from the vacuum chamber and etch it in a bath of wet chemicals, such as ammonium fluoride (NH.sub.4 F) and hydrofluoric acid (HF), or a combination of NH.sub.4 F, HF, and acetic acid. The wet etching process etches the various layers slightly differently, so that upon rinsing, cleaning, and re-inserting into a vacuum chamber, the different layers can be viewed. Unfortunately, the time required to perform the multitude of steps involved in this process makes it unsuitable for real-time process control. Moreover, the etching of a chemical bath cannot practically be limited to the area of interest; the entire wafer must be etched to increase the contrast in a cross section of a single device of interest.
It has also been found that plasma etching using gases such as CF.sub.4 and C.sub.4 F.sub.8, enhances the contrast between the layers that were exposed by focused ion beam milling. Plasma etching is performed in a plasma chamber associated with a plasma-generating device. As in the wet chemical process described above, it is necessary to remove the specimen from the FIB vacuum chamber, place it in the plasma chamber for etching, and then place it in another high vacuum imaging instrument, such as a scanning electron microscope, for observation. The time required to switch between machines makes the plasma etching process for contrast enhancement unsuitable for production support when process engineers need answers quickly to keep a fabrication line running smoothly.
FIB systems are also useful in the design stage of an integrated circuit. When a prototype integrated circuit is fabricated and tested, it is often found that changes to the circuit design are necessary. An FIB system can modify an integrated circuit, allowing changes to be implemented and tested without having to modify the photolithography masks and create a new prototype. Such changes are called "device edits." The FIB system can sever electrical connections by etching through conductors or create new connection by the selective deposition of conductive materials.
Modern circuits can use as many as twelve or more conductive metal layers, separated by insulators. In debugging a circuit design, it may be necessary to create connections between buried connectors. This can be done by FIB milling a hole, or "via," through the insulating layers above a conductor to expose the underlying conductor. When the underlying conductors are deeply buried, however, the material sputtered at the bottom of the hole during milling tends to redeposit on the side walls of the hole. Thus, it becomes impossible to mill a hole having a high aspect ratio, that is, a deep hole much deeper than it is wide. It is necessary, therefore, to mill a wide hole 2, as shown in FIG. 11, to expose a deep conductor 3. Unfortunately, with the dense packing of modern integrated circuits, a wide hole may damage circuitry on other layers, such as conductor 4.
To FIB mill a high aspect ratio hole 5 as shown in FIG. 12, XeF.sub.2 gas can be used to enhance the FIB etching of the inter layer dielectric. Unfortunately, XeF.sub.2 is highly toxic and very corrosive. Moreover, XeF.sub.2 etches copper, which is becoming widely used as a conductor in the fabrication of integrated circuits, because of its high conductivity. It is difficult to etch through an IDL using XeF.sub.2 to a copper conductor without etching and significantly degrading the exposed copper conductors, which then exhibit increased resistivity and can render the rewiring of the circuit ineffective. FIG. 12 shows that by using XeF.sub.2, conductor 4 is undamaged, but conductor 3 is inadvertently etched by the XeF.sub.2 gas and significantly reduced in the cross section, and therefore increased in resistivity.